Consider the cache memory and the main memory connected serially. If the word in not found in cache memory, then it is found in the main memory. Let C1 and C2 be the cache memory in a two-level cache system. The access time of C1 is 3 cycle, access time of C2 is 15 cycle and the access time of main memory is 50 cycle. The miss rate of is 10% and 20% of C1 and C2 respectively. The average memory access time of the system is _____ cycle.