A pipelined processor executing with a constant clock rate has 5 stages. The five stages are Fetch, Decode, Execute, Memory Access and Write Back.  Latency of the stages are 100, 80, 120, 150 and 140 nanoseconds respectively. If a register which has a delay of 10 ns is used between the different stages of the pipelined processor. The time taken to execute 2001 instruction for a pipelined processor is _____ microseconds.