railway RRB JE (CBT I + CBT II) Mock Test 2024 Digital Electronics Sequential Circuits Memory Elements
What is the frequency and duty cycle of output Y, when CLK frequency is 1 MHz @50% duty cycle?
1
500 kHz @ 50% duty cycle
2
500 kHz @ 25% duty cycle
3
250 kHz @ 50% duty cycle
4
250 kHz @ 25% duty cycle