If we use internal data forwarding to speed up the performance of a CPU (R1, R2 and R3 are registers and M[100] is a memory reference), then the sequence of operations
R1 → M[100]
M[100] → R2
M[100] → R3
Can be replaced by
1
R1 → R3
R2 → M[100]
2
M[100] → R2
R1 → R2
R1 → R33
R1 → M[100]
R2 → R34
R1 →R2
R1 → R3
R1 → M[100]5
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