Teaching UGC NET Mock Test Series 2025 (Paper 1 & 2) Computer Organization and Architecture Instruction Pipelining Instruction Pipeline
Comprehension Passage
Consider an unpipelined machine with a 10-nanosecond clock cycle, in which ALU operations and branches each require four cycles, while memory operations take five cycles. The relative frequencies of these operations are 40%, 20%, and 40%, respectively. Accounting for clock skew and pipeline setup, let us assume the machine adds a one-nanosecond overhead to the clock cycle.
Including the 1 nsec overhead due to clock skew and setup, what is the clock cycle time of the pipelined machine?
1
10 nsec
2
11 nsec
3
12 nsec
4
13 nsec