Consider the following statements:
(i) In burst mode DMA, the CPU can be put on hold while the DMA transfer occurs and a full block can be moved.
(ii) In transparent mode, the DMA controller transfers data only when the CPU is performing operations that do not use the system buses.
(iii) In cycle stealing mode only one word of data transferred in a single request.
Which of the above statement/s is/are TRUE ?
1
(i) only
2
(ii) and (iii) only
3
(iii) only
4
All are true