Teaching UGC NET Mock Test Series 2025 (Paper 1 & 2) Computer Organization and Architecture Instruction Pipelining Instruction Pipeline
A 5 stage pipeline is used to overlap all the instructions except the branch instructions .the target of the branch can’t be fetched till the current instruction is completed .each stage is having same amount of delay .the pipeline clock is 10 ns and the branch penality is 4 cycles.
What is the speedup of the system if 20 % of the instructions are branch instructions.1
2.8
2
2.9
3
3.0
4
3.2