Teaching UGC NET Mock Test Series 2025 (Paper 1 & 2) Computer Organization and Architecture Instruction Pipelining Instruction Pipeline
A CPU has a 5-stage pipeline with the following stages Fetch (F), Decode (D), Execute (E), Memory (M) and Write-back (W). Each stage takes one clock cycle to complete. Assume there are no pipeline stalls and the pipeline is initially empty. How many clock cycles are required to complete the execution of 10 instructions?
1
10
2
14
3
15
4
19